法国Karay推出256核并行芯片 目标定位图像处理

专为嵌入式应用开发 MPPA 多核处理器的无晶圆厂IC设计公司Kalray SA近日宣布,现可开始提供内含256颗处理器核心的 28nm MPPA-256晶片样品。

该处理器据称能以较其它处理器更低的功耗提供每秒高达5,000亿次的运算处理性能。该元件主要针对图像处理、信号处理、控制、通讯以及数据安全等嵌入式应用。

MPPA-256 晶片设计主要由Kalray与台湾创意电子(Global Unichip Corp.)携手合作,并由台积电进行制造。

Kalray宣布第一批投入量产的产品是针对图像应用的处理器。预计在2012年11月完成产品合格认证。

Kalray公司成立于2008年,是由法国投资基金、地方基金、私人投资者和法国公共部门机构OSEO共同资助;该公司CEO Joel Monnier曾任意法半导体(ST Microelectronics)研发副总裁。Kalray在2008年7月成立时已募得超过2,000万美元的创投资金。该公司并声称至今已累积45项专利组合。

Kalray处理器核心采用专有的 VLIW 架构与先进的低功耗设计技术,并整合高性能IEEE 754浮点单元。 MPPA-256 的256个处理器以16颗为一个单元组成16个丛集排列,通过晶片内的网络彼此通讯,如同网络上大型电脑集群一样。多个 MPPA 晶片可通过 Interlaken 总线在PCB板级实现互连,以提高处理器阵列的规模与性能。

除了 MPPA 处理器以外,Kalray并为客户提供了软件开发环境,称为 AccessCore 。Kaleay还提供 GNU C / C++ 开发工具与软件库,包括任务和数据平行基础。 AccessCore 开发环境提供一个基于C语言的编程模型,包括 Linux 支持的传统功能,以及更高层次的数据环境。标准 GCC 和 GDB 技术用于编译与除错。

Kalray在一份声明中说:「Kalray的技术持续与几个垂直市场的多家OEM夥伴以及第三方软件供应商共同开发,」Kalray公司CEO Joel Monnier在一份声明中表示。「我们的第一款处理器实现了每秒5,000亿次运算的全域处理性能,而其功耗也较竞争解决方案更低。」

LONDON – Kalray SA, the well-supported French launching a parallel processing chip and software, has 25 customers and is hopeful of winning more in Germany and Japan, according to CEO Joel Monnier.

Monnier told EE Times that the 28-nm MPPA-256 processor from Kalray (Orsay, France), with its 16 clusters of 16 VLIW processors on-chip, is well-suited to imaging applications such as graphics computation and image recognition and is also being used as a platform for video compression and transcoding.

High Efficiency Video Coding (HEVC) is a video standard, currently being developed by a joint team between MPEG and VCEG. The finalized HEVC standard is expected to bring 50 percent bitrate savings compared to equivalent H.264/AVC encodings. HEVC should be ready for ratification by ISO and ITU as H.265 by the end of January 2013.

For broadcast applications algorithms such advanced codings are typically done on FPGAs but Monnier said that MPPA-256 processor die size is smaller than leading FPGAs and more power efficient for such tasks. “We also have a very good position in augmented reality,” said Monnier, who prior to serving Kalray was corporate vice president at STMicroelectronics NV in charge of R&D from 1989 to 2004.

Kalray has just announced that it can supply samples of the 28-nm MPPA-256 processor and Monnier said that the chips would be in use by customers before the end of the year. “We have 25 customers developing applications based on Kalray. This is mainly in Europe because of close relationships in France. We have good prospects in Japan and we want to be in the United States in the first quarter of 2013.”

Other applications include signal processing of various types, including military tasks, data security support and scientific applications. Other applications such as EDA software acceleration are under discussion, Monnier said.

Monnier stressed that although Kalray is just starting out in a number of professional-class applications where chip volumes are not as large as in consumer applications its foundry supplier TSMC has been very supportive. “We are not a small volume chip company although it may take one, two, three years to become accepted in different markets,” Monnier said. “We started out two years ago with MPW [multiproject wafer] runs to do test circuits but this chip [MPPA-256] is based on a full mask set for Kalray.

Monnier said he did not regret leaving off a mainstream processor, such as an ARM core for housekeeping, off the chip or to ease integration with other computational units. “It’s not an issue for Kalray. Linux is running on the processor,” he said. He added that the software development support that makes MPPA-256 easy to use and program is an important part of the company’s offering. “We have a C-like language for dataflow applications and can run it intermixed with C/C++ routines. The chip also has ample I/O channels including multiple DDR, PCI and Interlaken interfaces.

But that could expose one problem. It may be hard for the MPPA-256 to achieve its theoretical maximum performance of 500-GOPS with the quoted typical 5-W power consumption. Monnier admitted that with all the I/O going there could be instantaneous demands that would push the device. “Everything going at full speed could be 30 to 40 watts,” he said.

Kalray has a roadmap that includes the MPPA-512 and MPPA-1024 chips with corresponding increases in the processing core count but he declined to forecast when, or in what process technology, they would arrive. Instead he emphasized derivatives of the MPPA-256. “There will be some derivatives of the basic product to make them more specific for different applications.

Kalray is also expecting to make sales of board-level and boxed products that can act as accelerators for connection to a desktop computer or server.

“Early next year we will offer a Kalray developer board with one MPPA-256 with an Intel motherboard as a development tool for customers. Another board will have multiple MPPA chips, a minimum of four, maybe six,” said Monnier. After nearly four years in development sales traction for the 50-person team will, no doubt, be welcome.

《DPI Vendors Deliver on Policy Management》厂商目录节译

from HeavyReading DPI Vendors Deliver on Policy Management,Google翻译+修改

平台:以下公司提供策略管理系统,包含高性能的DPI,分类和策略执行软件。 Allot通信有限公司 ( ALLT )和Procera Networks公司 (PKT )基于ATCA平台提供策略执行系统。 这些系统使用x86多核处理器和网络处理器或基于MIPS的多核处理器的组合。 Bivio网络公司和Sandvine公司基于专有平台提供策略体系。 这些系统集成了混合的PowerPC,MIPS和/或基于x86多核处理器。 ipoque公司系统采用专有或IBM公司的 BladeCenter平台。

芯片:英特尔是x86多核处理器的领先供应商,其策略管理系统具有新的数据平面软件和支持高速接口支持的新芯片组,市场份额不断增长。 AMD也提供多达16个处理器内核的x86多核处理器。 Cavium网络公司 ( CAVM )和博通公司(BRCM )-最近收购了NetLogic公司 ,提供一系列高性能的多核处理器,集成了多达48个 MIPS内核和许多包处理硬件加速引擎,基于PowerPC的多核处理器主要有飞思卡尔半导体公司和LSI公司 。 EZchip(EZCH ), Netronome公司和Tilera公司提供具有很多数据包处理引擎和高速接口的网络处理器。

软件:软件是任何策略管理解决方案的一个重要组成部分。 BroadHop公司 , Qosmos , Sensory网络公司和Volubill供应策略管理软件,可以移植到一系列多核处理器架构,包括x86,MIPS和PowerPC。 6WIND和Vineyard网络的提供协议栈和软件开发工具包,帮助系统制造商开发的策略管理解决方案。

Adapteva:小公司有大野心

初创公司Adapteva宣布将推出一种新的芯片架构,借助于全新的生产工艺,这种处理器将拥有4000个小核心,远远超出现有的PC处理器核心数量。国内媒体的报导似乎有些走样,变成了Adapteve成为击败x86,ARM的超级杀手,但实际上这家公司目前的定位还只是特定功能的协处理器。

大部分的移动处理器生产商努力提高每瓦能耗下的MIPS(注:每秒百万条指令)值,这是最常用的功率利用率的评估方式。但是Adapteva公司准备另辟蹊径:增加每瓦能耗下的每秒浮点运算次数(FLOPS)值。这个袖珍初创公司已经开发并测试了一个能够提供业界领先的每瓦FLOPS值的独特架构。虽然有些人认为浮点(FP)性能只对超级计算机和特殊的信号处理应用有效,但是这种类型的强力FP引擎也许很快就会进入你我的智能手机中。

Epiphany多核架构

Adapteva公司提供其Epiphany多核架构为IP核,根据不同性能等级可做裁剪。最基本的16核设计达到每瓦峰值速率为19GFLOPS。在2mm2面积情况下,这个设计对典型的移动应用处理器成本影响有限。配置为协处理器时,Epihpany在典型移动设备的一定功耗范围内能大幅提升浮点处理能力。

以下是苹果设备采用的A5芯片,绿色部分为Epiphany内核所占空间。

为什么移动设备需要如此高的处理能力?对于普通的语音到文本的转换功能,许多先进的语音识别算法依赖于浮点特性;视觉计算有助于基于手势的游戏,高级的用户接口,增强现实技术(AR),甚至提升健康和安全。Adapteva的架构可以满足语音识别和视觉计算所需的性能要求。

虽然Epiphany架构比起同等浮点性能水平的CPU或者GPU所需的晶圆面积要小,但是高端移动处理器已经有了CPU(或许集成了ARM公司的Neon加速器)和GPU,由此用CPU/GPU来执行浮点密集的任务无需增加任何面积。这是Adapteva公司面临的一个主要问题。另外,在忍受Epiphany额外的芯片成本和设计周期之前,预计移动芯片商会等待FP的应用模型更加成熟。不过如果视觉计算成为用户界面和应用软件的一部分,浮点加速器将会和我们现在看到的视频加速器一样普遍,Adapteva就会成为差异化竞争的好榜样。

Adapteva公司从2008年成立到现在只花费了150万美金。低成本运作的秘诀就在于使用免费的开源软件并且只雇用了四名在一起共事超过十年的全职员工。翻看管理层介绍就会发现这家公司其实就是ADI公司的TigerSHARC DSP产品线的前架构师带领余部创立,而所谓的十年共事经验应该就是指在ADI公司的那段经历。从管理层的求学经历来看这个team似乎都不超过40岁,年轻有为!

美国PartMiner公司停止运营 IHS收购核心资产

据外电报道,美国当地时间3月15日,有内部人士透露分销商PartMiner停止了其全球业务运营。很明显,客户对此还一无所知。

消息表示这一过程不会很快,但是结果确定。

ParMiner公司还没有正式公布这一计划。另外,位于科罗拉多的总机号码录音显示电话已经停止服务。

3月5日,这家公司刚刚宣布其CAPS (Computer Assisted Product Selection)数据库和工具被IHS收购。

国产申威HPC放异彩 多核DSP不甘寂寞

上月国内首台全部采用国产中央处理器(CPU)和系统软件构建的千万亿次计算机系统引起不小轰动,外媒也大肆报道中国在HPC以及CPU领域的进展。装机8704片16核的“申威1600”处理器,由国家高性能集成电路(上海)设计中心自主研发,采用自主指令集,济南中心神威蓝光系统性能功耗比超过741MFLOPS/W(每瓦功耗所获取的运算性能)。不过据悉申威是在DEC alpha ISA的基础上发展而来,我国有关部门江南所多年改进而来。

长久以来CPU,GPU始终是HPC设计的不二选择,不过最近TI公司突然发现本为4G通信而在DSP中加入的浮点运算单元可能使其DSP产品线成为高性能计算领域的强有力竞争者。TI公司多核DSP商务经理Friedmann表示最新一代多核处理器完全胜任HPC需求,问题只在于应用实现的完美程度。

胜任这一伟大使命的是TI公司于2010年11月最新推出的TMS320C66x系列DSP,40nm工艺,有单核,双核,四核以及八核规格。与前一代C64x系统只支持定点运算相比,C66x增加了4G通信处理所需的浮点指令。架构基于TI最新的KeyStone,包括8阶VLIW架构,高速交换架构TeraNet,多核调度以及DMA引擎。用于数据和指令的L1 Cache 32KB,每核有专有L2 Cache 512KB。对于主频1.25GHz的8核C66x,单精度Gigaflops为160,功耗仅为10W,即16 SP gigaflops/watt.

据Friedmann介绍,已经有“相当多”的大学和商业HPC客户对DSP技术产生兴趣并安排人手移植应用,TI公司专门成立HPC部门。
第一款适用于HPC的C66x产品将是由4个运行在1GHz主频的八核DSP组成的PCIe板块,由Advantech代工的这块半长PCIe板卡功耗为50W,提供 512 SP gigaflops性能。板载内存大小为4G 1.333GHz DDR3 Memory。Nvidia最新的Tesla 20系列板卡功耗为225W,性能为1331 SP gigaflops,两者的性能/瓦特比分别为10和6。对比双精度运算,TI DSP性能为单精度性能的3/8,Tesla GPU则为1/2。总体来讲,TI DSP在能耗方面都更胜一筹。也许随着Nvidia在2012年推出Kepler,Intel在2013年推出Many Integrated Core (MIC)协处理器以后会提供性能/瓦特比更高的产品,但是TI应该也会相应推出升级产品。

一个待解的问题是如何在DSP上开发HPC风格的软件。

好在DSP与GPU和FPGA不同,它与CPU近似,TI的DSP不需要特殊的编程语言也无需主处理器驱动。通过传统的C语言工具,配套OpenMP或者MPI,整套应用都可以跑在DSP核上。TI的软件开发套件已经提供必备工具,包括C编译器,runtime以及对浮点运算和并行编程的支持。

TI的HPC部门也意识到同Intel和Nvidia成熟的并行编程环境相比还需要提升自身的软件工具,所以如果客户需要,TI甚至考虑移植OpenCL到DSP中。

目前TI的一个8-10人小团队正在基于最新的DSP做benchmark测试并移植一些潜在客户的代码,他们希望能展现出DSP在HPC领域的潜力,同这个领域的主流厂家Intel,Nvidia,AMD一决高下。

AlcaLu 400G网络处理器诞生的背后

ALU上月底宣布推出具有突破性的400G网络处理器FP3,从100G的FP2到400G的FP3,ALU在2003年收购的TiMetra团队再次立下战

功。从芯片角度看FP3大幅领先于专业网络处理器供应商如Ezchip/Xelerated;从产品角度看,基于FP3的7750业务路由器在端

口能力上将达到2 Tbit/s,不仅追赶上竞争对手并且基于FP3芯片的方案所需芯片数目更少,从功耗,板面积,成本方面都有更大的优势。

FP3是由网络处理器和流量管理器组成的两颗套片。如此给力领先的设计是高端数字芯片设计合作的一个完美范例,因为这颗芯片并不是ALU独立从零开始完成一切从前端到后端的设计,这颗芯片的诞生离不开ALU合作伙伴的支持。

ALU的新闻稿表明,FP3设计得到了Broadcom,Cypress,GSI,Micron,Netlogic和Samsung的大力支持。在内存以及内存接口方面,Cypress,GSI,Micron,Netlogic和Samsung等TCAM,Memory专业厂家应该提供了各自的IP core,博通在高速设计和接口方面应该发挥了最重要的作用。

早在TiMetra年代Broadcom就投资并与TiMetra在交换架构上有深入合作,如今再次联手,博通为ALU工程师提供了设计所需的很多工具,从设计软件工具到关键部分的IP core,比如Serdes,博通一共为ALU设计提供了100多个定制库。由此ALU的IP division总裁Basil Alwan认为Broadcom是ALU的“Foundry”。虽然Broadcom没有晶圆厂,并不作芯片生产代工服务,但这表明了Broadcom在这颗芯片中发挥的重要作用。

FP3的推出也带来了两个有意思的问题:

对于设备商来讲,高端芯片是采用商用产品还是自研?Cisco目前与Ezchip合作高端网络处理器,Juniper自家有Trio,华为在自研Solar,但是高端设备的发货量是否足以支撑如此大的投入,尤其是在45nm,28nm时代需要巨大投片成本的情况下。

传统上LSI/TI/IBM/Avago等厂家有提供芯片设计服务的业务,Broadcom是否也有进入这个业务领域的冲动?Broadcom的IP core数量和质量应该足以支撑博通进入这个领域。

EZchip公布更多200G网络处理器细节

网络处理器专业厂商EZchip公司公布了其下一代NP-5处理器的细节。NP-5网络处理器(NPU)处理能力将为200G,内置200G的流量管理单元,这将有效降低交换机/路由器的10GE, 40GE和100GE线卡的密度。同时正在设计中的NP-5将为现在使用NP-4 100G芯片的用户提供升级路径,代码后向兼容NP-4,由此在很少软件工作量的情况下客户可以将线卡的带宽和端口密度翻倍。

NP-4采用55nm工艺,计划于2011年下半年进入量产阶段。NP-5将采用28nm工艺,计划于2012年底推出样片。

EZchip公司将在Linley Tech于6月7-8号在美国加州举办的运营商大会上介绍NP-5。

NP-5的主要特性包括:

  • 200-Gigabit programmable packet processing
  • Integrated 200-Gigabit hierarchical traffic management
  • Ethernet ports with integrated MACs supporting 48×10-Gigabit / 12 x 40-Gigabit / 4×100-Gigabit interfaces or combinations thereof
  • Enhanced memory management for lookup tables, packet buffering and statistics, all using commodity DDR3 devices for minimized cost and power
  • Integrated fabric adaptor for interfacing to Ethernet-based switch-fabrics and 10GBase-KR links for direct connection to the system’s backplane
  • Power management for minimizing line card and system power dissipation
  • Enhanced support for video streams and IPTV
  • On-chip control CPU for host CPU offload
  • Operations, Administration and Management (OAM) processing offload
  • Synchronous Ethernet and IEEE1588v2 offload for Circuit Emulation Services
  • IP reassembly for advanced packet processing offload

众巨头聚首 开放虚拟化联盟成立

本周二,在San Francisco旧金山举行的开源商务大会上,HP (HPQ), IBM, Intel (INTC), BMC Software (BMC), Red Hat (RHT), Eucalyptus Systems和SUSE联合宣布成立开放虚拟化联盟,旨在推动开源的虚拟化技术的应用,包括基于内核的虚拟机(KVM)。

对开源社区的补充

开放联盟将会为各种商务应用提供培训,实践和技术指导,同时也会为负责KVM程序和相关管理程序开发的开源社区提供补充支持。他们也会鼓励互通并围绕KVM加速第三方生态系统的扩展。大概从2007年起,KVM虚拟化开始利用Intel和AMD处理器原生支持来构建稳健高效的Linux和Windows虚拟机。

共同的目标

开放虚拟化联盟的成员在助力开放虚拟化方面都有共同的目标,因为这会使他们的客户有机会选择与自身商业应用最匹配的虚拟化产品。SPECvirt_sc2010基准测试是用来评估整个系统(包括硬件,虚拟化平台以及虚拟化的子操作系统和应用软件)端到端性能的工具,HP,IBM和红帽都拥有很多关于SPECvirt_sc2010基准测试的记录。

成员发言

红帽VP,云业务经理Scott Crenshaw表示:当一家公司独大霸占产业将会损害重新,客户成为冤大头。红帽和联盟旨在打破封闭的虚拟化,为客户提供更佳的性价比。

HP公司VP Paul Miller表示:有了联盟支持的核心虚拟机将会提供更多灵活性,与HP的产品架构兼容。

Rochester公司重建LSI公司CMOS ASIC门阵列产品线

罗彻斯特电子公司(Rochester Electronics)作为全球最大的停产和成熟半导体产品的授权生产商和分销商,宣布会继续提供LSI公司的HCMOS(高速互补型金属氧化物半导体) ASIC门阵列产品的生产服务。有了LSI公司的授权,罗彻斯特可以重建并生产完整的硅栅HCMOS工艺逻辑阵列产品,包括从3到0.35微米间9种工艺节点的1000多种产品设计。

罗彻斯特重建此产品线可以避免客户重新进行代价昂贵的系统设计,目前已经完成验证了LSI如下产品线:2-micron LL7000 channeled gate array series (CMOS7K Series), 1.0-micron LCA100K channel-free gate array series, 0.6-micron LCA300K channel-free gate array series, 0.50-micron LCA500K channel-free gate array series, and 0.35-micron G10 cell-based series.

LSI将会提供给罗彻斯特公司门阵列产品IP和数百种存档的设计数据库,通过罗彻斯特的半导体复型流程(SRP)就可以继续提供某些授权产品。罗彻斯特公司先进的SRP综合了存档认证,样品拆解,工艺匹配,源目标对比,SPICE分析以及对原厂家规范的验证等等。这一流程将保证罗彻斯特生产的器件完全与LSI原门阵列产品保持外形,尺寸和功能的一致。

Rochester公司号称生产2万多种从民用到航天航空级的各种封装形式的半导体元器件产品。此番重建的虽然是老旧工艺,但是可见依然在军工,航天和工业领域有长久应用,利润可期。LSI从80年代起家就在搞的技术又开出了新花。

附LSI与Agere合并前的milestone,现在网站上只有简化版

2006
•LSI announces ZEVIO™ processor architecture for consumer market. ZEVIO speeds time-to-market and enables low-cost, low-power 3D graphics and sound features for consumer electronics products.
•LSI and YesVideo introduce integrated DVD recorder software for indexing video content.
•LSI will focus on business growth opportunities in information storage and consumer markets.
•LSI first to demo Serial Attached SCSI (SAS) switch.

2005
•United States Patent and Trademark Office awards LSI its 3,000th patent.
•LSI announces new leadership team; will focus on primary markets (custom integrated circuits, consumer products, and storage platforms and products); Abhi Talwalkar named LSI president and CEO.

2004
•LSI introduces industry’s first single-chip 3 Gb/s Serial Attached SCSI (SAS) controller IC.
•Seagate Technology demonstrates the LSI RapidChip Platform ASIC technology in its Savvio (Savvy I/O) family of 2.5-inch enterprise-class disc drives.

2003
•LSI introduces industry’s first single-chip hard disk drive (HDD) and DVD recorder processor, the DoMiNo® 8650, for use in dual-drive digital recorders.
•LSI achieves 80 percent market penetration with its Ultra320 SCSI server controller, garnering key design wins with major OEMs.
•LSI partners with Beijing E-world to develop technologies for new high-definition format in China called EVD (enhanced versatile disc).

2002
•LSI introduces the G90™ 90-nanometer ASIC process technology, built upon a process platform jointly defined by LSI and TSMC.
•LSI becomes the first company to make a full line of Ultra320 SCSI host bus adapters (HBAs) available commercially.
•LSI introduces innovative semiconductor platform, RapidChip®.

2001
•LSI acquires consumer market leader C-Cube Microsystems Inc. in an accretive stock-for-stock transaction valued at $851 million.

2000
•LSI introduces industry’s first dual-channel PCI to Fibre Channel integrated controller featuring 2 Giga Baud data rates per channel.
•LSI announces Gflx™ 0.13-micron ASIC process technology, which offers 78 million usable logic gates.

1999
•Sony Computer Entertainment selects LSI to supply key I/O processor for its next generation PlayStation video game system, featuring 100 percent backward compatibility to the first PlayStation.

1998
•LSI introduces its G12™ ASIC 0.18-micron process technology, offering up to 26 million usable logic gates on a single chip.

1997
•LSI unveils G11™ 0.25-micron ASIC process technology, offering more than 8 million usable gates.
•The BBC selects LSI to develop a single-chip digital terrestrial television solution.
•LSI wins an Emmy Award for developing a real-time estimation encoder for General Instruments Corporation (now Next Level Systems).

1996
•LSI announces industry’s first Fibre Channel core, with automated control functions for disk drives, RAID arrays, Internet servers, video-on-demand, imaging and transaction processing.
•LSI announces industry’s first 1.25-billion bit-per-second CMOS serial transceiver, the GigaBlaze™ G10 SeriaLink® Core.

1995
•LSI introduces a new generation of ASIC process technology, the G10™ series, offering up to 5 million usable gates.

1994
•Sony Computer Entertainment introduces the PlayStation® video game system, featuring the LSI system-on-a-chip capability and using the company’s CoreWare design program.

1993
•LSI introduces 0.5-micron ASIC technology, capable of integrating up to nine million transistors on a single chip.
•CoreWare methodology is utilized to develop the LSI ATMizer™, the industry’s first single-chip reprogrammable solution for asynchronous transfer mode networking.

1992
•LSI introduces CoreWare® design program, a new approach to developing systems and building complete electronic systems on a single chip.
•LSI delivers the industry’s first RISC microcontroller with floating-point capability on-chip; target is cost-sensitive embedded applications where power and space are critical.

1991
•LSI develops JPEG (still picture), MPEG (full-motion video), and video-teleconferencing products for digital video markets.
•LSI participates in two HDTV (high definition television) projects in Japan. (Only U.S. company selected.)
•LSI introduces the industry’s first single-chip embedded graphics controller, targeting high-performance graphics applications.

1989
•LSI listed on the New York Stock Exchange under the symbol LSI.
•World’s first all-ASIC workstation is produced based on LSI technology.

1988
•LSI becomes the only semiconductor company to offer 32-bit RISC microprocessors for both MIPS and SPARC (Scalable Processor ARChitecture).
•LSI LCB007 becomes the industry’s first cell-based custom ASIC capable of integrating 200,000 gates on a single chip.

1986
•LCB15 Series cell-based ASIC family offers high density and performance and rivals full custom design methodologies. Based on 1.5-micron HCMOS process technology.
•LSI introduces its first standard product line, including 32-bit and 16-bit multipliers, 16-bit multiplier accumulators and 32-bit floating-point processors.

1985
•LSI announces LCA10000 Compacted Array Family, with 50,000 available gates.

1984
•LL8000 Series 2-micron gate array product family introduced.

1983
•LSI becomes public company with initial offering of $152 million; common stock is traded on NASDAQ as LLSI.
•LSI introduces concept of regional ASIC engineering design centers, bringing service closer to customers

1982
•LL3000 Series CMOS Gate Array (3.5 micron, 2,500 gates) announced.
•LL5000 Series (3-micron, 2-layer metal) introduced.

1981
•LSI Logic Corporation founded; designs semiconductors customized to the specific application requirements of customers. ASIC (application specific integrated circuit) market emerges.
•LC3100 Series of CMOS arrays (1,782 gates) announced.